Developing a modern processor is extremely challenging due to the complexity of its design. We therefore aim to provide advanced processor performance modeling and design methodologies, to reduce the costs and efforts of proposing and validating a new processor design.
Fast and accurate performance modeling
To design a next-generation processor, architects must analyze the current designs to identify critical bottlenecks and the corresponding problems. In this process, the performance model of a processor design determines the analysis costs (i.e., time and computing power) as well as the result quality (i.e., accuracy of performance/bottleneck analysis). Our main goal is to develop a model which quickly produces performance analysis results without compromising the accuracy.
Efficient design methodology
Upon identifying problems, architects develop new processor designs by adding their ideas. However, for complex modern processor designs, the number of new design candidates are typically large and validating each design also takes a significant amount of time. Therefore, we focus on reducing the design validation overhead as well as the number of design candidates, to ultimately reduce the processor development efforts/costs.
⋅ RpStacks: Fast and Accurate Processor Design Space Exploration Using Representative Stall-Event Stacks
Published in the 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO ’14)
In this paper, we proposed RpStacks, a fast and accurate design space exploration method to identify key performance bottlenecks and make correct predictions on processor performance using a single simulation. RpStacks delivers highly accurate performance predictions by accounting hidden performance-critical paths, and enables agile architecture design evaluation. The fast and accurate prediction of RpStacks saves architects of time-consuming simulation steps, ultimately accelerating the processor development cycle.