One paper is accepted to ASPLOS 2020
D. Min et al., “CryoCache: A Fast, Large, and Cost-Effective Cache Architecture for Cryogenic Computing”, ASPLOS 2020 (to appear)
Two papers are accepted to MICRO 2019
M. Ajdari et al., “FIDR: A Scalable Storage System for Fine-Grain Inline Data Reduction with Efficient Memory Handling”, MICRO 2019
E. Baek et al., “FlexLearn: Fast and Highly Efficient Brain Simulations Using Flexible On-Chip Learning”, MICRO 2019
Two papers are accepted to ISCA 2019
G. Lee et al., “Cryogenic Computer Architecture Modeling with Memory-Side Case Studies”, ISCA 2019
H. Jang et al., “MnnFast: A Fast and Scalable System Architecture for Memory-Augmented Neural Networks”, ISCA 2019
One paper is accepted to EuroSys 2019
Y. Kim et al., “μLayer: Low Latency On-Device Inference Using Cooperative Single-Layer Acceleration and Processor-Friendly Quantization”, to appear in EuroSys 2019
One paper is accepted to HPCA 2019
M. Ajdari et al., “CIDR: A Cost-Effective In-line Data Reduction System for Terabit-per-Second Scale SSD Arrays”, HPCA 2019
Two papers are accepted to MICRO 2018
H. Jang et al., “RpStacks-MT: A High-throughput Multi-core Processor Design Evaluation Methodology”, MICRO 2018
J. Kim et al., “SSDcheck: Timely and Accurate Prediction of Irregular Behaviors in Black-Box SSDs”, MICRO 2018
One paper is accepted to USENIX ATC 2018
D. Chae et al., “DynaMix: Dynamic Mobile Device Integration for Efficient Cross-device Resource Sharing,” to appear in Proc. 2018 USENIX Annual Technical Conference (USENIX ATC), July 2018.
Two papers are accepted to ISCA 2018
D. Kwon et al., “DCS-ctrl: A Fast and Flexible Device-Control Mechanism for Device-Centric Server Architecture”, ISCA 2018
D. Lee et al., “Flexon: A Flexible Digital Neuron for Efficient Spiking Neural Network Simulations”, ISCA 2018
Two papers are accepted to ASPLOS 2018
J. Lee et al., “WSMeter: A Performance Evaluation Methodology for Google’s Production Warehouse-Scale Computers”, ASPLOS 2018
A. Boroumand et al., “Google Workloads for Consumer Devices: Mitigating Data Movement Bottlenecks”, ASPLOS 2018
Two papers are accepted to IEEE CAL 2018
M. Ajdari et al., “A Scalable HW-Based Inline Deduplication for SSD Arrays”, IEEE CAL Jan. 2018
J. Kim et al., “SSD Performance Modeling Using Bottleneck Analysis”, IEEE CAL Jan. 2018